bernardo/MARTe2-isttok
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Changed RT DMA buffs

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Signed-off-by: Bernardo Carvalho <bernardo.carvalho@tecnico.ulisboa.pt>
This commit is contained in:
Bernardo Carvalho
2024-05-02 16:28:50 +01:00
parent d62dc8a082
commit 06f9a6d851
3 changed files with 168 additions and 137 deletions
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17
Analysis/calcDriftMds.py
View File

@@ -12,16 +12,25 @@ import argparse
ADC_CHANNELS = 14 # channels stored in ISTTOK
DECIM_RATE = 200
MDSTREENAME = 'rtappisttok'
def main(args):
mdsPulseNumber = args.shot
mdsTreeName = 'rtappisttok'
try:
tree = Tree(mdsTreeName, mdsPulseNumber)
if(mdsPulseNumber > 0):
tree = Tree(MDSTREENAME, mdsPulseNumber)
else:
tree = Tree(MDSTREENAME)
mdsPulseNumber = tree.getCurrent()
tree.close()
tree = Tree(MDSTREENAME, mdsPulseNumber)
except:
print(f'Failed opening {mdsTreeName} for pulse number {mdsPulseNumber:d}')
print(f'Failed opening {MDSTREENAME} for pulse number {mdsPulseNumber:d}')
exit()
print(f'Openpening {MDSTREENAME} for pulse number {mdsPulseNumber:d}')
# add plt.addLegend() BEFORE you create the curves.
#mdsNode = tree.getNode("ATCAIOP1.ADC0RAW")
#dataAdc = mdsNode.getData().data()
@@ -59,7 +68,7 @@ if __name__ == '__main__':
#parser.add_argument('-l','--list', nargs='+')
parser.add_argument('-c', '--crange', nargs='+',type=int, help='Channel plots (1 12)',default=[1, 12])
parser.add_argument('-i', '--irange', nargs='+',type=int,default=[1, 12])
parser.add_argument('-s', '--shot', type=int, help='Mds+ pulse Number ([1, ...])', default=100)
parser.add_argument('-s', '--shot', type=int, help='Mds+ pulse Number ([1, ...])', default=0)
#parser.add_argument('-e', '--averages', action='store_true', help='Calc averages')
#parser.add_argument('-w', '--drift', action='store_true', help='Calc drifts')
#, default='')

91
DataSources/AtcaIop/AtcaIopADC.cpp
View File

@@ -46,32 +46,47 @@
/*---------------------------------------------------------------------------*/
namespace MARTe {
//const float64 ADC_SIMULATOR_PI = 3.14159265359;
const uint32 IOP_ADC_OFFSET = 2u; // in DMA Data packet in 32b. First 2 are counter.
const uint32 IOP_ADC_INTEG_OFFSET = 16u; // in 64 bit words
//const float64 ADC_SIMULATOR_PI = 3.14159265359;
const uint32 IOP_ADC_OFFSET = 2u; // in DMA Data packet in 32b. First 2 are counter.
const uint32 IOP_ADC_INTEG_OFFSET = 16u; // in 64 bit words
const uint32 RT_PCKT_SIZE = 1024u;
const uint32 RT_PCKT64_SIZE = 512u; // In 64 bit words
const uint32 RT_PCKT_SIZE = 1024u;
const uint32 RT_PCKT64_SIZE = 512u; // In 64 bit words
/* 256 + 3840 = 4096 B (PAGE_SIZE) data packet*/
typedef struct _DMA_CH1_PCKT {
/* 256 + 3840 = 4096 B (PAGE_SIZE) data packet
typedef struct _DMA_CH1_PCKT {
uint32 head_time_cnt;
uint32 header; // h5431BACD
int32 channel[60]; // 24 56
uint32 foot_time_cnt;
uint32 footer; // h9876ABDC
uint8 page_fill[3840];
} DMA_CH1_PCKT;
} DMA_CH1_PCKT;
*/
#define DMA_RT_PCKT_SIZE 256
/* 256 Bytes RT data packet */
typedef struct _DMA_CH1_PCKT {
volatile uint32_t head_time_cnt;
volatile uint32_t header; // h5431BACD
volatile int32_t adc_decim_data[ADC_CHANNELS];
volatile uint64_t _fill64_0; // 00
volatile int64_t adc_integ_data[ADC_CHANNELS];
volatile int64_t _fill64_1[4]; // 00
volatile uint32_t sample_cnt;
volatile uint32_t _fill32; // hAAAABBBB
volatile uint32_t foot_time_cnt;
volatile uint32_t footer; // h9876ABDC
} DMA_CH1_PCKT;
struct atca_eo_config {
struct atca_eo_config {
int32_t offset[ATCA_IOP_MAX_CHANNELS];
};
};
struct atca_wo_config {
struct atca_wo_config {
int32_t offset[ATCA_IOP_MAX_CHANNELS];
};
};
//}
//}
/*---------------------------------------------------------------------------*/
/* Method definitions */
@@ -110,7 +125,7 @@ AtcaIopADC::AtcaIopADC() :
if (!synchSem.Create()) {
REPORT_ERROR(ErrorManagement::FatalError, "Could not create EventSem.");
}
}
}
/*lint -e{1551} the destructor must guarantee that the Timer SingleThreadService is stopped.*/
AtcaIopADC::~AtcaIopADC() {
@@ -388,13 +403,13 @@ bool AtcaIopADC::SetConfiguredDatabase(StructuredDataI& data) {
}
//mappedDmaBase = (int32 *) mmap(0, getpagesize() * NUMBER_OF_BUFFERS,
mappedDmaBase = (int32 *) mmap(0, 4096u * NUMBER_OF_BUFFERS,
mappedDmaSize = getpagesize();
mappedDmaBase = mmap(0, mappedDmaSize, //4096u, // * NUMBER_OF_BUFFERS,
PROT_READ, MAP_SHARED, boardDmaDescriptor, 0);
if (mappedDmaBase == MAP_FAILED){
ok = false;
REPORT_ERROR(ErrorManagement::FatalError, "Error Mapping DMA Memory Device %s", fullDeviceName);
}
mappedDmaSize = getpagesize();
uint32 statusReg = 0;
int rc = ioctl(boardFileDescriptor, ATCA_PCIE_IOPT_DMA_RESET);
@@ -469,7 +484,7 @@ bool AtcaIopADC::SetConfiguredDatabase(StructuredDataI& data) {
bool isCounter = false;
bool isTime = false;
bool isAdc = false;
// bool isAdcDecim = false;
// bool isAdcDecim = false;
//bool isAdcSim = false;
uint32 signalIdx = 0u;
uint32 nSamples = 0u;
@@ -551,7 +566,7 @@ bool AtcaIopADC::SetConfiguredDatabase(StructuredDataI& data) {
timerPeriodUsecTime = static_cast<uint32>(periodUsec);
float64 sleepTimeT = (static_cast<float64>(HighResolutionTimer::Frequency()) / cycleFrequency);
sleepTimeTicks = static_cast<uint64>(sleepTimeT);
/*
/*
* [Information - AtcaIopADC.cpp:548]: The timer will be set using a cycle frequency of 10000.000000 Hz
* [Information - AtcaIopADC.cpp:554]: The timer will be set using a sleepTimeTicks of 100000 (ns)
*/
@@ -640,6 +655,7 @@ bool AtcaIopADC::PrepareNextState(const char8* const currentStateName, const cha
/*lint -e{715} [MISRA C++ Rule 0-1-11], [MISRA C++ Rule 0-1-12]. Justification: the method sleeps for the given period irrespectively of the input info.*/
ErrorManagement::ErrorType AtcaIopADC::Execute(ExecutionInfo& info) {
DMA_CH1_PCKT *pdma = (DMA_CH1_PCKT *) mappedDmaBase;
if (lastTimeTicks == 0u) {
lastTimeTicks = HighResolutionTimer::Counter();
}
@@ -693,18 +709,20 @@ ErrorManagement::ErrorType AtcaIopADC::Execute(ExecutionInfo& info) {
ErrorManagement::ErrorType err = synchSem.Post();
counterAndTimer[0] += nCycles;
//counterAndTimer[1] = counterAndTimer[0] * timerPeriodUsecTime;
counterAndTimer[1] = mappedDmaBase[oldestBufferIdx * RT_PCKT_SIZE] * timerPeriodUsecTime;
//counterAndTimer[1] = mappedDmaBase[oldestBufferIdx * RT_PCKT_SIZE] * timerPeriodUsecTime;
counterAndTimer[1] = pdma[oldestBufferIdx].head_time_cnt * timerPeriodUsecTime;
// Get adc data from DMA packet
uint32 k;
uint32 s;
for (k=0u; k < ATCA_IOP_N_ADCs ; k++) {
adcValues[k] = (mappedDmaBase[oldestBufferIdx * RT_PCKT_SIZE +
IOP_ADC_OFFSET + k] ) / (1<<14);
//adcValues[k] = (mappedDmaBase[oldestBufferIdx * RT_PCKT_SIZE +
// IOP_ADC_OFFSET + k] ) / (1<<14);
adcValues[k] = pdma[oldestBufferIdx].adc_decim_data[k] / (1<<14);
}
int64 * mappedDmaBase64 = (int64 *) mappedDmaBase;
//int64 * mappedDmaBase64 = (int64 *) mappedDmaBase;
for (k=0u; k < ATCA_IOP_N_INTEGRALS ; k++) {
adcIntegralValues[k] = mappedDmaBase64[oldestBufferIdx * RT_PCKT64_SIZE + IOP_ADC_INTEG_OFFSET + k];
adcIntegralValues[k] = pdma[oldestBufferIdx].adc_integ_data[k];
//mappedDmaBase64[oldestBufferIdx * RT_PCKT64_SIZE + IOP_ADC_INTEG_OFFSET + k];
}
float64 t = counterAndTimer[1];
@@ -729,33 +747,36 @@ uint32 AtcaIopADC::GetSleepPercentage() const {
* */
int32 AtcaIopADC::PollDma(uint64 waitLimitTicks) const {
uint32 buffIdx = oldestBufferIdx;
uint32 oldBufferFooter = mappedDmaBase[buffIdx * RT_PCKT_SIZE + 62];
uint32 freshBufferFooter = oldBufferFooter;
//uint32 oldBufferFooter = mappedDmaBase[buffIdx * RT_PCKT_SIZE + 62];
DMA_CH1_PCKT *pdma = (DMA_CH1_PCKT *) mappedDmaBase;
uint32 oldBufferFooter = pdma[oldestBufferIdx].foot_time_cnt;
volatile uint32 freshBufferFooter = oldBufferFooter;
//uint32 buffIdx = oldestBufferIdx;
uint64 actualTime = HighResolutionTimer::Counter();
while (freshBufferFooter == oldBufferFooter) {
if(actualTime > waitLimitTicks) {
return -1;
}
actualTime = HighResolutionTimer::Counter();
freshBufferFooter = mappedDmaBase[buffIdx * RT_PCKT_SIZE + 62];
//freshBufferFooter = mappedDmaBase[buffIdx * RT_PCKT_SIZE + 62];
freshBufferFooter = pdma[oldestBufferIdx].foot_time_cnt;
}
uint32 headTimeMark = mappedDmaBase[buffIdx * RT_PCKT_SIZE];
//uint32 headTimeMark = mappedDmaBase[buffIdx * RT_PCKT_SIZE];
uint32 headTimeMark = pdma[oldestBufferIdx].head_time_cnt ;
if(headTimeMark != freshBufferFooter)
{
//currentBufferIdx = buffIdx;
//currentMasterHeader = pdma[currentBufferIdx].head_time_cnt;
return -2;
}
return buffIdx;
return oldestBufferIdx;
}
uint32 AtcaIopADC::GetOldestBufferIdx() const {
volatile uint32 oldestBufferHeader = mappedDmaBase[0];
DMA_CH1_PCKT *pdma = (DMA_CH1_PCKT *) mappedDmaBase;
uint32 buffIdx = 0u;
volatile uint32 header = mappedDmaBase[0];
volatile uint32 header = pdma[buffIdx].head_time_cnt;
volatile uint32 oldestBufferHeader = header;
for (uint32 dmaIndex = 1u; dmaIndex < NUMBER_OF_BUFFERS; dmaIndex++) {
header = mappedDmaBase[dmaIndex * RT_PCKT_SIZE];
header = pdma[dmaIndex].head_time_cnt;
if (header < oldestBufferHeader) {
oldestBufferHeader = header;
buffIdx = dmaIndex;

3
DataSources/AtcaIop/AtcaIopADC.h
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@@ -401,7 +401,8 @@ namespace MARTe {
/**
* Pointer to mapped memory
*/
int32 * mappedDmaBase;
//int32 * mappedDmaBase;
void * mappedDmaBase;
uint32 mappedDmaSize;
/**
* The last written buffer